Addressing failures in exascale computing

Marc Snir is the Director of Argonne’s Mathematics and Computer Science Division and the Michael Faiman and Saburo Muroga Professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. His research is focused on HPC, with recent work on programming models, performance analysis, and resilience. Snir received his PhD from the Hebrew University of Jerusalem. He spent time at NYU, where he worked on the NYU Ultracomputer, and at IBM Research, where he led the research team that worked on the software for the IBM SP and Blue Gene systems. At UIUC, he headed the CS department and led the creation of the Illinois Informatics Institute. Marc Snir is an AAAS, ACM, IEEE, and Argonne Fellow. He has recently received the IEEE Award for Excellence in Scalable Computing and the IEEE Computer Society Seymour Cray Computer Engineering Award.

Pavan Balaji holds appointments as a Computer Scientist at the Argonne National Laboratory, as an Institute Fellow of the Northwestern-Argonne Institute of Science and Engineering at Northwestern University, and as a Research Fellow of the Computation Institute at the University of Chicago. He leads the Programming Models and Runtime Systems group at Argonne. His research interests include parallel programming models and runtime systems for communication and I/O, modern system architecture (multicore, accelerators, complex memory subsystems, high-speed networks), and cloud computing systems. He has nearly 100 publications in these areas and has delivered nearly 120 talks and tutorials at various conferences and research institutes. He is a recipient of several awards including the U.S. Department of Energy Early Career award in 2012, TEDx Midwest Emerging Leader award in 2013, Crain’s Chicago 40 under 40 award in 2012, Los Alamos National Laboratory Director’s Technical Achievement award in 2005, Ohio State University Outstanding Researcher award in 2005, five best-paper awards, and various others. He serves as the worldwide chairperson for the IEEE Technical Committee on Scalable Computing (TCSC). He has also served as a chair or editor for nearly 50 journals, conferences, and workshops, and as a technical program committee member in numerous conferences and workshops. He is a senior member of the IEEE and a professional member of the ACM. More details are available at http://www.mcs.anl.gov/~balaji.

Todd Munson received a BS in Computer Science from the University of Nebraska in 1995, and an MS in 1996 and PhD in 2000 in Computer Science from the University of Wisconsin at Madison. He is a Computational Scientist in the Mathematics and Computer Science Division at Argonne National Laboratory, a Senior Fellow in the Computation Institute at the University of Chicago and Argonne National Laboratory. The primary focus of his research is algorithms and applications of numerical optimization and variational inequalities. He has been widely recognized for his contributions. Among other honors he was awarded a Presidential Early Career Award for Scientists and Engineers from the White House, an Early Career Scientist and Engineer Award from the U.S. Department of Energy in 2006, and the Beale-Orchard-Hayes Prize from the Mathematical Programming Society in 2003. He has twice been invited to the White House to meet the President of the United States (Bush 41 and Bush 43).

Andrew A Chien is the William Eckhardt Professor in Computer Science at the University of Chicago. He is also a Senior Fellow at UC’s Computation Institute and a Senior Computer Scientist at Argonne National Laboratory. His research interests include parallel computing, computer architecture, and cloud computing. From 2005 to 2010, Chien was Vice President of Research at Intel Corporation where he launched new initiatives in parallel software, mobile computing, cloud computing, and exascale research. From 1998 to 2005, Chien was the SAIC Endowed Chair Professor in the Department of Computer Science and Engineering where he founded the Center for Networked Systems at the University of California San Diego. From 1990 to 1998, he was a Professor of Computer Science at the University of Illinois at Urbana-Champaign and the National Center for Supercomputing Applications (NCSA). He has served on numerous advisory committees for the National Science Foundation, Department of Energy, and universities such as Stanford, EPFL, and Cal-Berkeley. Chien earned BS, MS, and PhD degrees at the Massachusetts Institute of Technology, and is a Fellow of the ACM, IEEE, and AAAS.

Pradip Bose is a research scientist at IBM T. J. Watson Research Center, where he manages a department on power-efficient, resilient systems. He holds a PhD from the University of Illinois at Urbana-Champaign. He has been associated with the definition and pre-silicon modeling of virtually all POWER-series processors, beginning with the original pre-product super scalar RISC project at IBM. He is a member of IBM’s Academy of Technology and an IEEE Fellow.

Al Geist is a Corporate Research Fellow at Oak Ridge National Laboratory. He is the Chief Technology Officer of the Leadership Computing Facility. His recent research is on exascale computing and resilience needs of hardware and software.

Saurabh Bagchi is a Professor in the School of Electrical and Computer Engineering and the Department of Computer Science (by courtesy) at Purdue University in West Lafayette, Indiana. He is a Senior Member of IEEE and ACM, a Distinguished Speaker for ACM, an IMPACT Faculty Fellow at Purdue (2013–14), and an Assistant Director of the CERIAS security center at Purdue. He leads the Dependable Computing Systems Laboratory (DCSL), where his group performs research in practical system design and implementation of dependable distributed systems. Since 2011, he has been serving as a Visiting Scientist with IBM Austin Research Lab.

Mattan Erez is an Associate Professor at the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research focuses on improving the performance, efficiency, and scalability of computing systems through advances in hardware architecture, software systems, and programming models. The vision is to increase the cooperation across system layers and develop flexible and adaptive mechanisms for proportional resource usage. Erez received a BSc in Electrical Engineering and a BA in Physics from the Technion, Israel Institute of Technology, and his MS and PhD in Electrical Engineering from Stanford University.

Sarita V Adve is Professor in Computer Science at the University of Illinois. Her research interests are broadly in computer architecture and systems. She leads the SWAT project, one of the early projects to explore holistic software-driven solutions for hardware resiliency. She is an ACM Fellow, an IEEE Fellow, and an ABI Women of Vision award winner in innovation.

Sven Leyffer is a senior computational mathematician in the Mathematics and Computer Science Division at Argonne National Laboratory, and a Senior Fellow of the Computation Institute. He obtained his PhD from the University of Dundee, UK, and has held postdoc positions at Dundee, Northwestern University, and Argonne. He is a Fellow of the Society for Industrial and Applied Mathematics.

Nathan DeBardeleben received his PhD in Computer Engineering from Clemson University in 2004 and started at Los Alamos National Laboratory the same year. DeBardeleben has been influential in defining the field of HPC resilience, its challenges and potentials. He has co-authored a handful of governmental position papers on the subject as well as his own research publications. In his own research, his focus is on characterizing the impact of soft errors on systems and applications. DeBardeleben is on numerous reliability program committees, runs his own workshop (Fault-tolerance for HPC at Extreme Scale (FTXS)) and runs the Los Alamos National Laboratory resilience site (http://institute.lanl.gov/resilience/).

Christian Engelmann is Task Lead of the System Software Team in the Computer Science and Mathematics Division at Oak Ridge National Laboratory. He earned his PhD in Computer Science in 2008 and his MSc in Computer Science in 2001, both from the University of Reading, UK. He also obtained a German Certified Engineer diploma in Computer Systems Engineering in 2001 from the University of Applied Sciences, Berlin. Engelmann’s research aims at computer science challenges for extreme-scale HPC system software, such as dependability, scalability, and portability. His primary expertise is in HPC resilience, that is, providing efficiency and correctness in the presence of faults, errors, and failures through avoidance, masking, and recovery. His secondary expertise is in HPC hardware/software co-design through lightweight simulation of extreme-scale systems with millions of processor cores to study the impact of hardware properties on parallel application performance.

Jim Belak is a senior scientist in the Condensed Matter and Materials Division at Lawrence Livermore National Laboratory. He is Co-PI and Deputy Director for the Exascale Co-design Center for Materials in Extreme Conditions (ExMatEx), a joint project with Los Alamos National Laboratory, ORNL, SNL-A, Stanford, and CalTech, funded by the DOE Office of Advanced Scientific Computing Research. The goal of ExMatEx is to use the supercomputer codes used to study matter under extreme conditions to guide the design of future supercomputers and use the understanding gained to refactor and create new supercomputer codes. He earned his PhD in Condensed Matter Physics from Colorado State University.

Fred Johnson is currently with SAIC serving as senior SAIC technical advisor to the DOE NNSA Advanced Simulation & Computing organization. He has retired as the Senior Technical Manager for Computer Science in DOE/ASCR where he was the Program Manager responsible for fundamental computer science research and research on high-performance system software and tools including programming models, debugging and performance evaluation tools, software component architectures for high-performance systems, and next-generation runtime and OSs.

Pedro Diniz earned his PhD from the University of California, Santa Barbara, in Computer Science in 1997. Since then he has been a Research Assistant Professor of Computer Science with the University of Southern California in Los Angeles, California. He has also been involved in several research projects focusing on programming technology and execution models addressing productivity-related issues as well as fault-tolerance for large-scale high-performance architectures. He has participated in various scientific proposal review boards at the National Science Foundation as well as at the European Commission in Brussels. Over the last 20 years he has been heavily involved in the scientific community having participated as part of the technical program committee of over 15 international conferences in the area of HPC, reconfigurable and field-programmable computing.

Paul Coteus is an IBM Fellow in the Systems Department at the Thomas J. Watson Research Center. Coteus completed his PhD in Physics at Columbia University and joined IBM in 1988, leaving his position as Assistant Professor of Physics at the University of Colorado. He has directed and designed advanced packaging for high-speed electronics, memory systems, and processor complexes. He is currently the Chief Engineer of Data Centric Systems, and also leads the system engineering for the full line of Blue Gene Supercomputers, honored in 2008 with the National Medal of Technology and Innovation. He is an IEEE Fellow, a member of IBM’s Academy of Technology, and an IBM Master Inventor. He has authored more than 90 papers in the field of electronic packaging, and holds over 120 US patents.

Rinku Gupta is a senior scientific developer at Argonne National Laboratory. She received her MS degree in Computer Science from Ohio State University in 2002. She has several years of experience developing systems and infrastructure for enterprise HPC. Her research interests primarily lie towards middleware libraries, programming models, and designing fault-tolerance frameworks in HEC systems. More details about her are available at http://www.mcs.anl.gov/~rgupta.

Franck Cappello holds a Senior Computer Scientist position at Argonne National Laboratory where he leads the resilience effort. He is the main PI of the G8 ‘Enabling Climate Simulation at Extreme Scale’ project gathering research groups from six countries. He is also the initiator and co-director of the INRIA-Illinois-ANL Joint Laboratory on Petascale Computing. Before moving to USA, he led the Grand-Large and Grid’5000 projects in France at INRIA, focusing on high-performance issues and research methodology for large-scale distributed systems. He has authored more than 130 papers and contributed to more than 70 program committees. He is an editorial board member of the international Journal of Grid Computing, Journal of Grid and Utility Computing, and Journal of Cluster Computing. He served in the steering committees of IEEE HPDC and IEEE/ACM CCGRID. He is the Program Co-Chair of ACM HPDC 2014 and ACM CAC 2014.

Rob Schreiber is a Distinguished Technologist at Hewlett Packard Laboratories. Schreiber’s research spans sequential and parallel algorithms for matrix computation, compiler optimization for parallel languages, and high-performance computer design. With Moler and Gilbert, he developed the sparse matrix extension of Matlab. He created the NAS CG parallel benchmark. He was a designer of the High Performance Fortran language. At HP, he led the development of PICO, a system for synthesis of custom hardware accelerators. His recent work concerns architectural uses of CMOS nanophotonic communication and NVM architecture. He is an ACM Fellow, a SIAM Fellow, and was awarded, in 2012, the Career Prize from the SIAM Activity Group in Supercomputing.

Dean Liberty is a Fellow at Advanced Micro Devices (AMD). He leads the Reliability/Availability/Serviceability (RAS) Architecture and Strategy team, focusing on long-term planning, detailed architecture, and short-term implementation for resilience in AMD processors. Dean has been in the computer industry for over 30 years, and involved in HPC systems for over 20 years. His experience covers a range of hardware and software, and his interests lie in bridging the gap between the two.

Eric Van Hensbergen is currently a principal design engineer at ARM Research in Austin, Texas. His current research focuses on exploring energy-efficient approaches to HPC through balance-driven co-design. Previous to ARM he was a research staff member in the Future Systems department at IBM’s Austin Research Lab. Over 12 years at IBM Research, he worked on distributed OSs for HPC, low-power dense server and network processor appliance blades, DRAM power management, full system simulation, HPC, hypervisors, and the Linux OS. Before coming to IBM, he worked for four years at Lucent Technologies Bell Laboratories on the Plan 9 and Inferno OSs.

Sriram Krishnamoorthy received his BE degree from the College of Engineering-Guindy, Anna University, Chennai, and his MS and PhD degrees from The Ohio State University, Columbus, Ohio. He is currently a research scientist at Pacific Northwest National Laboratory. His research focuses on parallel programming models, fault tolerance, and compile-time/runtime optimizations for HPC. He has over 60 peer-reviewed conference and journal publications, receiving best-paper awards for his publications at the International Conference on High Performance Computing (HiPC’03) and the International Parallel and Distributed Processing Symposium (IPDPS’04). He is a recipient of the U.S. Department of Energy Early Career award and Pacific Northwest National Laboratory’s Ronald L. Brodzinski Award for Early Career Exceptional Achievement in 2013. He is a senior member of the IEEE and a professional member of ACM.

Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel Corporation. His research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His research results have seen widespread proliferation in industry, and have been recognized by several prestigious awards including the Presidential Early Career Award for Scientists and Engineers from the White House, the Intel Achievement Award, Intel’s highest corporate honor, and several best-paper awards for publications at major conferences and journals. He is a Fellow of the IEEE.

Jon Stearley is a senior member of technical staff at Sandia National Laboratories. His interests include historical and live mining of system logs to identify the root causes of faults, the propagation of errors, and their effects on user jobs, towards faster fixes today and better designs tomorrow.

Saverio Fazzari works for Booz Allen acting as a senior technical advisor to DARPA and other government agencies for numerous programs. Fazzari has a strong background in all areas of semi-conductor design and fabrication, from algorithm development through device implementation. His specialty is advanced circuit design and development strategies with a focus on hardware cyber security issues including trusted design and fabrication. His experience includes extensive commercial experience, leading production innovation and development across all facets of the electronic design process.

Jacob A Abraham is a Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. He is also director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received a bachelor degree in Electrical Engineering from the University of Kerala, India, in 1970. His MS degree, in Electrical Engineering, and PhD, in Electrical Engineering and Computer Science, were received from Stanford University, California, in 1971 and 1974, respectively. From 1975 to 1988 he was on the faculty of the University of Illinois, Urbana, Illinois.

William Carlson is a member of the research Computing Sciences Staff at the IDA Center for Computing Sciences where, since 1990, his focus has been on applications and system tools for large-scale parallel and distributed computers. He also leads the UPC Language Effort, a consortium of industry and academic research institutions aiming to produce a unified approach to parallel C programming based on global address space methods. Carlson graduated from Worcester Polytechnic Institute in 1981 with a BS degree in Electrical Engineering. He then attended Purdue University, receiving MSEE and PhD degrees in Electrical Engineering in 1983 and 1988, respectively. From 1988 to 1990, Carlson was an Assistant Professor at the University of Wisconsin–Madison, where his work centered on performance evaluation of advanced computer architectures.

Robert W Wisniewski is an ACM Distinguished Scientist and the Chief Software Architect for Extreme-Scale Computing and a Senior Principal Engineer at Intel Corporation. He has published over 60 papers in the area of HPC, computer systems, and system performance, and has filed over 50 patents. Before coming to Intel, he was the chief software architect for Blue Gene Research and manager of the Blue Gene and exascale research software team at the IBM T.J. Watson Research Facility, where he was an IBM Master Inventor and lead the software effort on Blue Gene/Q, which was the fastest machine in the world on the June 2012 Top 500 list, and occupied four of the top 10 positions. Prior to working on Blue Gene, he worked on the K42 scalable OS project targeted at scalable next-generation servers and the DARPA HPCS project on continuous program optimization that utilizes integrated performance data to automatically improve application and system performance. Before joining IBM Research, and after receiving a PhD in Computer Science from the University of Rochester, he worked at Silicon Graphics on high-end parallel OS development, parallel real-time systems, and real-time performance monitoring.